Summary: <p>“You reach critical certain thresholds that are driven by the laws of physics and material science” – Perry Keller</p> <p>DDR5 marks a huge shift in thinking for traditional high-tech memory and IO engineering teams. The implications of this are just now being digested by the industry, and opening up doors for new technologies. In today’s electrical engineering podcast, Daniel Bogdanoff and Mike Hoffman sit down with Perry Keller to discuss how engineers should “get their game on” for DDR5.</p> <div class="jetpack-video-wrapper"></div> <p> </p> <p>Audio:</p> <audio class="wp-audio-shortcode" id="audio-1833-10" style="width: 100%;"><a href="https://eestalktech.com/wp-content/uploads/2018/04/ddr5-and-3d-silicon-ees-talk-tech-25.mp3">https://eestalktech.com/wp-content/uploads/2018/04/ddr5-and-3d-silicon-ees-talk-tech-25.mp3</a></audio> <p><a href="http://pages.electronicdesign.com/Digital-Design-Test">Sign up for the DDR5 Webcast</a> with Perry on April 24, 2018!</p> <h2>Agenda:</h2> <p>00:20 Getting your game on with DDR5</p> <p>LPDDR5 6.4 gigatransfers per second (GT/s)</p> <p>“You reach critical certain thresholds that are driven by the laws of physics and material science” – Perry Keller</p> <p>1:00 We’re running into the limits of what physics allows</p> <p>2:00 <a href="https://www.keysight.com/main/application.jspx?nid=-33352.0.00&lc=eng&cc=US">DDR3</a> at 1600 – the timing budget was starting to close.</p> <p>2:30 With DDR5, a whole new set of concepts need to be embraced.</p> <p>3:00 DesignCon is <em>the</em> trade show – Mike is famous for his picture with ChipHead</p> <p>4:00 Rick Eads talked about DesignCon in the <a href="http://eestalktech.com/2017/04/26/under-the-hood-of-pci-express/">PCIe</a> <a href="http://www.eestalktech.com">electrical engineering podcast</a></p> <p>4:40 The DDR5 paradigm shift is being slowly digested</p> <p>4:50 DDR (double data rate) introduced source synchronous clocking</p> <p>All the previous memories had a system clock that governed when data was transferred.</p> <p><a href="http://literature.cdn.keysight.com/litweb/pdf/5990-3575EN.pdf">Source synchronous clocking </a>is when the system controlling the data also controls the clock. Source synchronous clocking is also known as forward clocking.</p> <p>This was the start of high speed digital design.</p> <p>At 1600 Megatransfers per second (MT/s), this all started falling apart.</p> <p>For DDR5, you have to go from high speed digital design concepts to concepts in high speed serial systems, like USB.</p> <p>The reason is that you cant control the timing as tightly. So, you have to count on where the data eye is.</p> <p>As long as the receiver can follow where that data eye is, you can capture the information reliably.</p> <p>DRAM doesn’t use an embedded clock due to latency. There’s a lot of overhead, which reduces channel efficiency</p> <p>9:00<br> DDR is single ended for data, but over time more signals become differential.</p> <p>You can’t just drop High Speed Serial techniques into DDR and have it work.</p> <p>The problem is, the eye is closed. The old techniques won’t work anymore.</p> <p>10:45<br> DDR is the last remaining wide parallel communication system.</p> <p>There’s a controller on one end, which is the CPU. The other end is a memory device.</p> <p>11:15<br> With DDR5, the eye is closed. So, the receiver will play a bigger part. It’s important to understand the concepts of equalizing receivers.</p> <p>You have to think about how the controller and the receiver work together.</p> <p>12:20<br> Historically, the memory folks and IO folks have been different teams. The concepts were different. Now, those teams are merging</p> <p>13:00</p>
